Last week you designed an FIR filter in Matlab to remove noise from a speech wave. You examined the effect of quantisation on the response of the filter and decided on a suitable coefficient width to maintain the performance of your filter. This week you are provided with some examples of a simple FIR filter implemented in Verilog, along with a testbench. You will be required to analyse and implement a longer set of filter taps, attempting to minimise implementation cost without failing the performance requirements.
On completing this practical you will be able to:
Use and Analyse the Provided Filter
– You have been given a set of taps in signed integer form in filter_taps_integer.csv.
o You may assume that the original requirements for this filter were as follows:
– Analyse the provided taps:
o How many magnitude bits are needed to represent these taps?
o Pick fractional length to ensure the filter has an overall gain of 1.
o Provide the representation of the taps in signed/Q notation
o Calculate the group delay and transient length of this filter.
– In Matlab:
o Scale the taps such that they provide a gain of 1
o Get the frequency response of the taps, confirm the fc and the stopband attenuation
o For your report, apply the filter to a sinusoidal signal of amplitude 0.5, fsig = 0.1Fs.
▪ Plot the input and output in time domain and mark the transient response and group delay.
Examine the Provided FIR Structures
– The provided Verilog file fir_simple.v implements a simple 4 tap filter in a different structure to what we have observed in class.
o Draw a block diagram representing this 4 tap filter
o In your report, compare this to the structures examined during class. Which of these might provide higher throughput in your system? Justify your answer by calculating an upper limit for Fclk.
Implement the Provided Taps
– Using either of the filter structures provided (fir_simple.v or fir_simple_direct_form.v) as a starting point, implement the filter taps provided in filter_taps_integer.csv
Integrated Systems Design
– It is expected that you will make an effort to minimise the cost of your filter implementation, whilst still meeting the performance requirements of the filter. This should impact your filter structure, quantisation and how you handle bit-growth due to multiply-accumulate computations.
– Use the synthesis and implementation of FPGA resource utilisation reports in Vivado to compare the cost of your filter choices.
– Modify the provided testbench to provide the impulse response as a sanity check on your code.
Testing Implemented Filter Performance
– Extend your testbench to apply your test sinusoid from Matlab. You will need to scale the samples to be integers.
– You may modify the following code snippet to create a testbench that will read in filter input data and write out filter output data:
//openfile for input
//openfile for output
status = $fscanf(fd,”%d”, xn);
if(status == 0)begin
$finish; // couldn’t open file
end else if ($feof(fd)) begin
$finish; // reached end of file
end else begin
– Compare the output with results calculated in Matlab for the same sinusoid.
o Is the performance as expected? What finite word effects other than coefficient quantisation may be affecting performance?
– In your report comment on your handling of finite word effects in your RTL implementation, and how the choice of bit-growth handling can impact the overall quality of data in the system.
You must submit the following items in a zipped folder via Blackboard:
• All Matlab code
• Verilog project folder
• Any relevant timing diagrams/waveforms and Matlab plots.
• Short write-up named pract3p1_surnameinitial.pdf e.g. called pract3p1_WadeR.pdf. (Note the pdf format).